Microprocessors and other complex controllers and hubs are coupled to other components with electrical communications interconnections. These interconnections have names such as host bus, processor bus, front side bus, north bridge bus etc. One such interconnection interface is referred to as CSI (Common System Interface from Intel Corp.). When the components are all installed and plugged in, they communicate a wide variety of different messages over these interconnections. Link layer traffic may include power management and credit return messages or flits. The link layer is also typically responsible for ensuring that messages get transmitted and for recovering messages or flits that were not received correctly. Protocol layer traffic relates to higher level processes and are more easily controlled. While the messages may be important to operation of the equipment, they may interfere with testing and diagnosis of any one of the components. A test cycle or signal may be interrupted or its effect may be changed due to a message from or to another connected component.
For some microprocessor architectures new transactions may be blocked by asserting a specific pin or signal at a specific time. Earlier Intel architectures with a front side bus (FSB), have a BNR# signal to block new transactions. Alternatively, a BPRI# signal, may be used to block symmetric agents from issuing new transactions. However, only the priority agent can assert BPRI#, reducing its usefulness. For more generalized architectures, however, such a pin may not be available. In addition, the use of a pin for this process may increase the total number of pins on a chip, adding to its cost and complexity. Further, these approaches attempt to prevent new messages from being generated. Such an approach may be unreliable as new components or functions are added that may not respond to the prevention attempt.